1. Field of the Invention
The present invention relates generally to electrical circuits, and more particularly, to methods and apparatus for enabling an optimum amount of precharging time in a precharging operation.
2. Description of the Related Art
In memory circuits, current designs of precharge circuits can exhibit performance limitations when clocking signals are increased to a high level. As the clock frequency becomes faster and faster, the integrity of the precharge pulse shape/width becomes harder to maintain. Eventually, at high clock speeds, the precharge pulse width becomes too small to fully precharge the memory cells.
FIG. 1 shows a precharge circuit 100 with an array of memory cells organized in rows and columns. The first row 102 contains memory cells, such as, for example, cell 104, cell 106, and cell 108. The array contains a series of rows, such as second row 110 and so on. Memory cell 104 is connected to a bitline 112, indicated by a dash mark where memory cell 104 and bitline 112 intersect. As is well known, bitlines, such as bitline 112 allows the reading of the data stored in memory cell 104. Write bitlines, which may or may not be the same as bitline 112, would allow the writing of data to the memory cell 104. The memory cells located in the column formed below memory cell 104 are also connected to bitline 112. Bitline 112 is connected to sense amp 116 and precharge device 114 is attached to bitline 112. The precharge device 114 precharges the associated bitline 112.
As the clocking frequency of the system increases, problems can occur due to skew when the clock speed becomes higher as is typically desired. Therefore, problems may occur where there may not be enough time to properly precharge the bitlines due to the higher clock speeds. For example, if the clocking speed becomes very high, the bitlines may not be able to achieve the designed precharge voltage level.
In view of the foregoing, there is a need for memory designs and circuits for balancing precharge delivered to bitlines that couple to memory cells in banked architectures.